Visible to Intel only — GUID: bhc1411109442976
Ixiasoft
Introduction
System-Level Debugging Infrastructure
Virtual JTAG Interface Description
Run-Time Communication
Instantiating the Virtual JTAG Intel® FPGA IP Core
Simulation Support
Compiling the Design
SLD_NODE Discovery and Enumeration
Capturing the Virtual IR Instruction Register
AHDL Function Prototype
VHDL Component Declaration
VHDL LIBRARY-USE Declaration
Design Example: TAP Controller State Machine
Design Example: Modifying the DCFIFO Contents at Runtime
Design Example: Offloading Hardwired Revision Information
Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Visible to Intel only — GUID: bhc1411109442976
Ixiasoft
VHDL Component Declaration
The following VHDL component declaration is located in the ALTERA_MF_COMPONENTS.vhd file located in the < Intel® Quartus® Prime installation directory>\libraries\vhdl\altera_mf directory.
component sld_virtual_jtag
generic (
lpm_hint : string := "UNUSED";
lpm_type : string := "sld_virtual_jtag";
sld_auto_instance_index : string := "NO";
sld_instance_index : natural := 0;
sld_ir_width : natural := 1;
sld_sim_action : string := "UNUSED";
sld_sim_n_scan : natural := 0;
sld_sim_total_length : natural := 0 );
port(
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
ir_out: in std_logic_vector(sld_ir_width-1 downto 0);
jtag_state_cdr : out std_logic;
jtag_state_cir : out std_logic;
jtag_state_e1dr : out std_logic;
jtag_state_e1ir : out std_logic;
jtag_state_e2dr : out std_logic;
jtag_state_e2ir : out std_logic;
jtag_state_pdr : out std_logic;
jtag_state_pir : out std_logic;
jtag_state_rti : out std_logic;
jtag_state_sdr : out std_logic;
jtag_state_sdrs : out std_logic;
jtag_state_sir : out std_logic;
jtag_state_sirs : out std_logic;
jtag_state_tlr : out std_logic;
jtag_state_udr : out std_logic;
jtag_state_uir : out std_logic;
tck : out std_logic;
tdi : out std_logic;
tdo : in std_logic;
tms : out std_logic;
virtual_state_cdr : out std_logic;
virtual_state_cir : out std_logic;
virtual_state_e1dr : out std_logic;
virtual_state_e2dr : out std_logic;
virtual_state_pdr : out std_logic;
virtual_state_sdr : out std_logic;
virtual_state_udr : out std_logic;
virtual_state_uir : out std_logic
);
end component;
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