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Introduction
System-Level Debugging Infrastructure
Virtual JTAG Interface Description
Run-Time Communication
Instantiating the Virtual JTAG Intel® FPGA IP Core
Simulation Support
Compiling the Design
SLD_NODE Discovery and Enumeration
Capturing the Virtual IR Instruction Register
AHDL Function Prototype
VHDL Component Declaration
VHDL LIBRARY-USE Declaration
Design Example: TAP Controller State Machine
Design Example: Modifying the DCFIFO Contents at Runtime
Design Example: Offloading Hardwired Revision Information
Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Visible to Intel only — GUID: bhc1411109487322
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Configuring the JTAG User Code Setting
The following steps describe how to configure the JTAG User Code setting. A separate script generates the GUI and is executed with the quartus_stp command line executable. During runtime, the GUI queries the device for the version information and formats it for display within the message box.
- On the Assignment menu, click Settings.
- On the Settings page, in the Category list, click Device.
- The Device dialog box appears. Click Device and Pin Options.
- In the Device and Pin Options dialog box, on the General tab, the JTAG user code appears. Type the user code in 32-bit hexadecimal format.
- Click OK.
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