Virtual JTAG Intel® FPGA IP Core User Guide

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ID 683705
Date 8/12/2021
Public
Document Table of Contents
Document Table of Contents x
Virtual JTAG Intel® FPGA IP Core User Guide
Virtual JTAG Intel® FPGA IP Core User Guide x
Introduction System-Level Debugging Infrastructure Virtual JTAG Interface Description Run-Time Communication Instantiating the Virtual JTAG Intel® FPGA IP Core Simulation Support Compiling the Design SLD_NODE Discovery and Enumeration Capturing the Virtual IR Instruction Register AHDL Function Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration Design Example: TAP Controller State Machine Design Example: Modifying the DCFIFO Contents at Runtime Design Example: Offloading Hardwired Revision Information Document Revision History for the Virtual JTAG Intel® FPGA IP Core User Guide
Introduction x
Installing and Licensing Intel® FPGA IP Cores On-Chip Debugging Tool Suite Applications of the Virtual JTAG Intel® FPGA IP Core JTAG Protocol JTAG Circuitry Architecture
System-Level Debugging Infrastructure x
Transaction Model of the SLD Infrastructure SLD Hub Finite State Machine
Virtual JTAG Interface Description x
Input Ports Output Ports Parameters Design Flow of the Virtual JTAG Intel® FPGA IP Core Simulation Model Run-Time Communication Running a DR Shift Operation Through a Virtual JTAG Chain
Run-Time Communication x
Virtual IR/DR Shift Transaction without Returning Captured IR/DR Values Virtual IR/DR Shift Transaction that Captures Current VIR/VDR Values Reset Considerations when Using a Custom JTAG Controller
Instantiating the Virtual JTAG Intel® FPGA IP Core x
IP Catalog and Parameter Editor Specifying IP Core Parameters and Options Instantiating Directly in HDL
IP Catalog and Parameter Editor x
The Parameter Editor
Specifying IP Core Parameters and Options x
Files Generated for Intel® FPGA IP Cores (Legacy Parameter Editor)
Compiling the Design x
Third-Party Synthesis Support
SLD_NODE Discovery and Enumeration x
Issuing the HUB_INFO Instruction HUB IP Configuration Register SLD_NODE Info Register
Design Example: Modifying the DCFIFO Contents at Runtime x
Write Logic Read Logic Runtime Communication
Design Example: Offloading Hardwired Revision Information x
Configuring the JTAG User Code Setting
Virtual JTAG Intel® FPGA IP Core User Guide

SLD Hub Finite State Machine

The SLD hub decodes TMS independently from the hard JTAG TAP controller state machine and implements an equivalent state machine (called the “SLD hub finite state machine”) for the internal JTAG path. The SLD hub performs a similar function for the VIR and VDR chains that the TAP controller performs for the JTAG IR and DR chains. It enables an SLD node as the active path for the TDI pin, selects the TDI data between the VIR and VDR registers, controls the start and stop of any shift transactions, and controls the data flow between the parallel hold registers and the parallel shift registers of the VIR and VDR.

Because all shifts to VIR and VDR are encapsulated within a DR shift transaction, an additional control signal is necessary to select between the VIR and VDR data paths. The SLD hub uses the USER1 command to select the VIR data path and the USER0 command to select the VDR data path.

This state information, including a bank of enable signals, is forwarded to each of the SLD nodes. The SLD nodes perform the updates to the VIR and VDR according to the control states provided by the sld_hub. The SLD nodes are responsible for maintaining continuity between the TDI and TDO pins.

The figure below shows the SLD hub finite state machine. There is no direct state signal available to use for application design.

Figure 7. sld_hub Finite State Machine
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