System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
Intel® Cyclone® 10 GX Device Design Guidelines
|Intel® Quartus® Prime Design Suite 17.1|
This document provides a set of design guidelines, recommendations, and a list of factors to consider for designs that use Intel® FPGA (formerly Altera FPGA) Cyclone® 10 GX devices. This document also assists you with planning the FPGA and system early in the design process, which is crucial to successfully meet design requirements. For more information to help verify that you have followed each of the guidelines, use the “Design Checklist” topic in this app note.
Note: This application note does not include all Cyclone® 10 GX device details and features. For more information about Cyclone® 10 GX devices and features, refer to the " Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook".
The material references the Cyclone® 10 GX device architecture as well as aspects of the Intel® Quartus® Prime software and third-party tools that you might use in your design. The guidelines presented in this document can improve productivity and avoid common design pitfalls.
|Stages of the Design Flow||Guidelines|
|System Specification||Planning design specifications, IP selection|
|Device Selection||Device information, determining device variant and density, package offerings, migration, speed grade|
|Early System and Board Planning||Early power estimation, thermal management option, planning for configuration scheme, planning for on-chip debugging|
|Pin Connection Considerations for Board Design||Power-up, power pins, PLL connections, decoupling capacitors, configuration pins, signal integrity, board-level verification|
|I/O and Clock Planning||Pin assignments, early pin planning, I/O features and connections, memory interfaces, clock and PLL selection, simultaneous switching noise (SSN)|
|Design Entry||Coding styles and design recommendations, SOPC Builder, planning for hierarchical or team-based design|
|Design Implementation, Analysis, Optimization, and Verification||Synthesis tool, device utilization, messages, timing constraints and analysis, area and timing optimization, compilation time, verification, power analysis and optimization|
Figure 1. Cyclone® 10 GX Device Design Flow
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Implementation, Analysis, Optimization, and Verification
Appendix: Cyclone 10 GX Transceiver Design Guidelines
Document Revision History
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