System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
Configuration Scheme Selection
You can configure Cyclone® 10 GX devices with one of four configuration schemes:
- Fast passive parallel (FPP)—A controller supplies the configuration data in a parallel manner to the Cyclone® 10 GX FPGA. FPP is supported in an 8-bit (FPP ×8), 16-bit (FPP ×16) or 32-bit data width (FPP ×32).
- Active serial (AS)—The Cyclone® 10 GX FPGA controls the configuration process and gets the configuration data from a quad-serial configuration (EPCQL) device. AS is supported in 1-bit (AS ×1) or 4-bit data width (AS ×4).
- Passive serial (PS)—An external host supplies the configuration data serially to the Cyclone® 10 GX FPGA.
- Joint Test Action Group (JTAG)—Configured using the IEEE Standard 1149.1 interface with a download cable, or using MAX (MAX II, MAX V, MAX 10) devices, or microprocessor with flash memory.
You can enable any specific configuration scheme by driving the Cyclone® 10 GX device MSEL pins to specific values on the board.
|1||Select a configuration scheme to plan companion devices and board connections.|
All configuration schemes use a configuration device, a download cable, or an external controller (for example, MAX® ( MAX® II, MAX® V, Intel® MAX® 10) devices or microprocessor).
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