System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
Channel PLL (CMU/CDR PLL)
A channel PLL resides locally within each transceiver channel. Its primary function is clock and data recovery in the transceiver channel when the PLL is used in CDR mode. The channel PLLs of channel 1 and 4 can be used as a transmit PLL when reconfigured in CMU mode. The channel PLLs of channel 0, 2, 3, and 5 cannot be reconfigured in CMU mode and therefore cannot be used as a transmit PLL.
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