|1||Specify your formal verification tool and use the correct supported version.|
|2||If you use formal verification, check for support and design limitations.|
The Intel® Quartus® Prime software supports some formal verification flows. Using a formal verification flow can impact performance results because it requires that certain logic optimizations be turned off, such as register retiming, and forces hierarchy blocks to be preserved, which can restrict optimization. There are other restrictions that can also limit your design; consult the documentation for details.
If formal verification is important to your design, it is easier to plan for limitations and restrictions in the beginning than to make changes later in the design flow.
The " Intel® Quartus® Prime Pro Edition Software and Device Support Release Notes" list the version of each formal verification tool that is officially supported with that particular version of the Intel® Quartus® Prime software. Specify your formal verification tool in the EDA Tools Settings page of the Settings dialog box to generate the appropriate output netlist.
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