|1||Specify your simulation tool, and use the correct supported version and simulation models.|
The Intel® Quartus® Prime software supports both RTL and gate level functional simulations. Perform functional simulation at the beginning of your design flow to check the design functionality or logical behavior of each design block. You do not have to fully compile your design; you can generate a functional simulation netlist that does not contain timing information.
Intel provides the ModelSim* - Intel® FPGA Edition FPGA Starter Edition and offers the higher-performance ModelSim® - Intel FPGA Edition, which enable you to take advantage of advanced testbench capabilities and other features. In addition, the Intel® Quartus® Prime EDA Netlist Writer can generate timing netlist files to support other third-party simulation tools such as Synopsys VCS, Cadence NC-Sim, and Aldec Active-HDL. Specify your simulation tool in the EDA Tools Settings page of the Settings dialog box to generate the appropriate output simulation netlist. The software can also generate scripts to help you setup libraries in your tool with NativeLink integration.
If you use a third-party simulation tool, use the software version that is supported with your Intel® Quartus® Prime software version. The Intel® Quartus® Prime Software Release Notes list the version of each simulation tool that is officially supported with that particular version of the Intel® Quartus® Prime software. Use the model libraries provided with your Intel® Quartus® Prime software version, because libraries can change between versions, which might cause a mismatch with your simulation netlist. To create a testbench, on the Processing menu, point to Start and click Start Testbench Template Writer.
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