Intel® Cyclone® 10 GX Device Design Guidelines

ID 683703
Date 11/06/2017
Document Table of Contents

I/O Pin Count, LVDS Channels, and Package Offering

Cyclone® 10 GX devices are available in space-saving FineLine BGA packages with various I/O pin counts between 188 and 284 I/O pins. Determine the required number of I/O pins for your application, considering the design’s interface requirements with other system blocks.

Larger densities and package pin counts offer more full-duplex LVDS channels for different signaling; ensure that your device density-package combination includes enough LVDS channels. Other factors can also affect the number of I/O pins required for a design, including simultaneous switching noise (SSN) concerns, pin placement guidelines, pins used as dedicated inputs, I/O standard availability for each I/O bank, differences between I/O standards and speed for row and column I/O banks, and package migration options. For more information on choosing pin locations, refer to “Pin Connection Considerations for Board Design” and "I/O and Clock Planning"

You can compile any existing designs in the Intel® Quartus® Prime software to determine how many I/O pins are used. Also consider reserving I/O pins for debugging, as described in “Planning for On-Chip Debugging”.