Intel® Cyclone® 10 GX Device Design Guidelines

ID 683703
Date 11/06/2017
Document Table of Contents

DCLK and TCK Signal Integrity

The TCK and/or DCLK traces should produce clean signals with no overshoot, undershoot, or ringing. When designing the board, lay out the TCK and DCLK traces with the same techniques used to lay out a clock line. Any overshoot, undershoot, ringing, or other noise on the TCK signal can affect JTAG configuration. A noisy DCLK signal can affect configuration and cause a CRC error. For a chain of devices, noise on any of the TCK or DCLK pins in the chain could cause JTAG programming or configuration to fail for the entire chain.

Table 23.  DCLK and TCK Signal Integrity Checklist
Number Done? Checklist Item
1   Design configuration DCLK and TCK pins to be noise-free.