Intel® Cyclone® 10 GX Device Design Guidelines

ID 683703
Date 11/06/2017
Document Table of Contents

PLLs and Clock Routing

PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Cyclone® 10 GX device family contains the following PLLs:

  • Fractional PLLs—can function as fractional PLLs or integer PLLs
  • I/O PLLs—can only function as integer PLLs

The fractional PLLs are located adjacent to the transceiver blocks in the HSSI banks. Each HSSI bank consists of two fractional PLLs. You can configure each fractional PLL independently in conventional integer mode.

In fractional mode, the fractional PLL can operate with third-order delta-sigma modulation. Each fractional PLL has four C counter outputs and one L counter output. The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank consists of one I/O PLL. The I/O PLLs can operate in conventional integer mode. Each I/O PLL has nine C counter outputs.

Cyclone® 10 GX devices have up to 6 fractional PLLs and 6 I/O PLLs in the largest densities. Cyclone® 10 GX PLLs have different core analog structure and features support.

For more information about PLLs, refer to "PLLs and Clock Networks".