System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
The device speed grade affects the device timing performance and timing closure, as well as power utilization. There are two speed grades available: 5 (fastest) and 6. One way to determine which speed grade your design requires is to consider the supported clock rates for specific I/O interfaces.
You can use the fastest speed grade during prototyping to reduce compilation time (because less time is spent optimizing the design to meet timing requirements), and then move to a slower speed grade for production to reduce cost if the design meets its timing requirements.
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