System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
MSEL Configuration Mode Pins
|1||Connect the MSEL pins to select the configuration scheme; do not leave them floating.|
JTAG configuration is always available, regardless of the MSEL pin selection. The MSEL pins are powered by the VCCPGM power supply of the residing bank. The MSEL[2..0] pins have 25 kΩ internal pull-down resistors that are always active.
During POR and reconfiguration, the MSEL pins must be at LVTTL VIL and VIH levels to be considered a logic low and logic high, respectively. To avoid problems with detecting an incorrect configuration scheme, hardwire the MSEL pins to VCCPGM or GND without pull-up or pull-down resistors. Do not drive the MSEL pins with a microprocessor or another device.
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