System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
Clock Control Block
Every GCLK and RCLK network has its own clock control block. The control block provides the following features:
- Clock source selection (with dynamic selection for GCLKs)
- GCLK multiplexing
- Clock power down (with static or dynamic clock enable or disable)
Use these features to select different clock input signals or power-down clock networks to reduce power consumption without using any combinational logic in your design. In Cyclone® 10 GX devices, the clock enable signals are supported at the clock network level instead of at the PLL output counter level, so you can turn off a clock even when a PLL is not being used.
|1||Use the clock control block for clock selection and power-down.|
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