Intel® Cyclone® 10 GX Device Design Guidelines

ID 683703
Date 11/06/2017
Document Table of Contents

Clock Control Block

Every GCLK and RCLK network has its own clock control block. The control block provides the following features:

  • Clock source selection (with dynamic selection for GCLKs)
  • GCLK multiplexing
  • Clock power down (with static or dynamic clock enable or disable)

Use these features to select different clock input signals or power-down clock networks to reduce power consumption without using any combinational logic in your design. In Cyclone® 10 GX devices, the clock enable signals are supported at the clock network level instead of at the PLL output counter level, so you can turn off a clock even when a PLL is not being used.

Table 48.  Clock Control Features Checklist
Number Done? Checklist Item
1   Use the clock control block for clock selection and power-down.