System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
Using the Parallel Flash Loader Intel® FPGA IP with MAX Devices
|1||If you want to use a flash device with the parallel flash loader, check the list of supported devices.|
If your system already contains common flash interface (CFI) flash memory, you can utilize it for Cyclone® 10 GX device configuration storage as well. You can program CFI flash memory devices through the JTAG interface with the parallel flash loader (PFL) Intel® FPGA IP in MAX® II, MAX® V and Intel® MAX® 10 devices. The PFL also provides the logic to control configuration from the flash memory device to the Cyclone® 10 GX device and supports compression to reduce the size of your configuration data. Both PS and FPP configuration modes are supported using the PFL feature.
Did you find the information on this page useful?