Visible to Intel only — GUID: egm1488319332620
Ixiasoft
System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Design Checklist
Appendix: Cyclone® 10 GX Transceiver Design Guidelines
Conclusion
Document Revision History
Visible to Intel only — GUID: egm1488319332620
Ixiasoft
Voltage Reference Pins
Number | Done? | Checklist Item |
---|---|---|
1 | Design VREF pins to be noise-free. |
Voltage deviation on a VREF pin can affect the threshold sensitivity for inputs.
For more information about VREF pins and I/O standards, refer to “I/O Features and Pin Connections”.
Related Information
Did you find the information on this page useful?
Feedback Message
Characters remaining: