System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Design Checklist Appendix: Cyclone® 10 GX Transceiver Design Guidelines Conclusion Document Revision History
Board-Related Quartus Prime Settings
The Intel® Quartus® Prime software provides options for the FPGA I/O pins that you should consider during board design. Ensure that these options are set correctly when the Intel® Quartus® Prime project is created, and plan for the functionality during board design.
Device-Wide Output Enable Pin
Did you find the information on this page useful?