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System Specification
Device Selection
Early System and Board Planning
Pin Connection Considerations for Board Design
I/O and Clock Planning
Design Entry
Design Implementation, Analysis, Optimization, and Verification
Design Checklist
Appendix: Cyclone® 10 GX Transceiver Design Guidelines
Conclusion
Document Revision History
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Transceiver Phase-Locked Loops
Each transceiver channel in Cyclone® 10 GX devices has direct access to three types of high performance PLLs:
- Advanced Transmit (ATX) PLL
- Fractional PLL (fPLL)
- Channel PLL / Clock Multiplier Unit (CMU) PLL.
These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.
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