Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/02/2023

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Document Table of Contents Snapping to a Region

When placing Logic Lock regions in the Chip Planner by hand, Chip Planner is set to snap the placement of the region to adjacent LAB boundaries by default. This means that as you drag the region to a location, the region snaps to the adjacent lab boundary when you drop the region in the floorplan.

Alternatively, you can click View > Logic Lock Regions > Snap Logic Lock Region to to toggle the snapping between Snap to Lab or Snap to Clock Sector Region. When your turn on Snap to Clock Sector Region, orange grid lines appear to show the clock sector region boundaries when you create, resize, or move the region.

Figure 112. Snapped to the Region

  • Creating Region: Left-click on the mouse to create the Logic Lock region. Upon releasing the mouse, the created Logic Lock region snaps to the containing clock region or sector.
  • Resize region (and resize diagonal): Left-click on the mouse and drag the Logic Lock region handle. Upon releasing the mouse, the Logic Lock region resizes and snaps to the containing clock region or sector.
  • Move region: Select and drag the Logic Lock region to highlight the clock region boundaries. Upon releasing the mouse button, the Logic Lock region moves to the new position and snaps to the containing clock region or sector.
    • Same place and route regions are moved: Both Logic Lock regions move and snap to the containing clock sectors.
    • Only place | route region is moved: The selected region moves and snaps to the clock sector, and prompts warning if the new location or size of the region does not adhere to 'place bboxes contained within route bboxes' rule.
  • Subtract or make a hole: When performing subtract in the snap-to-clock-region mode, you create a region where the region is snapped to a clock region or a sector, and then subtract away.