Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/02/2023

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Document Table of Contents I/O Timing Constraints

Timing Analyzer supports the Synopsys* Design Constraints (SDC) format for constraining your design. When using the Timing Analyzer for timing analysis, use the set_input_delay constraint to specify the data arrival time at an input port with respect to a given clock. For output ports, use the set_output_delay command to specify the data arrival time at an output port’s receiver with respect to a given clock. You can use the report_timing Tcl command to generate the I/O timing reports.

The I/O paths that do not meet the required timing performance are reported as having negative slack and are highlighted in red in the Timing Analyzer Report pane. In cases where you do not apply an explicit I/O timing constraint to an I/O pin, the Intel® Quartus® Prime timing analysis software still reports the Actual number, which is the timing number that must be met for that timing parameter when the device runs in your system.