188.8.131.52. Guideline: Reduce Global Signal Congestion
For Intel® Stratix® 10 and Intel® Arria® 10 devices, you can refer to the generated Global Signal Visualization report to see global signal routing and clock sector utilization in an interactive heat map.
The presence of too many signals in a clock sector can result in congestion and routing failures in the Fitter's place stage. Use the Global Signal Visualization Report to debug global signal routing congestion and global signal placement and routing failures.
The interactive heat map shows the number of signals in use for a given clock sector. If these global signals are clocks, use clock region assignments to move clocks away from the affected clock sectors.