Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/02/2023

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Document Table of Contents

7.7. Analyzing and Optimizing the Design Floorplan Revision History

The following revision history applies to this chapter:

Table 43.  Document Revision History
Document Version Intel® Quartus® Prime Version Changes
2023.08.01 23.2
  • Replaced missing graphics in Analyzing Connections for a Path.
  • Replaced missing graphics in Navigating with the Bird's Eye View.
  • Replaced missing graphics in Viewing Immediate Fan-In and Fan-Out in Chip Planner.
  • Replaced missing graphics in Show Delays.
  • Replaced missing graphics in Starting the Chip Planner.
  • Replaced missing graphics in Adding a New Shape to a Logic Lock Region.
  • Replaced missing graphics in Creating Clock Assignments in Chip Planner.
  • Replaced missing graphics in Viewing Fan-In and Fan-Out in Chip Planner.
  • Replaced missing graphics in Viewing Design Connectivity and Hierarchy.
  • Replaced missing graphics in Subtracting Shape from Logic Lock Region.
2023.04.03 23.1
  • Updated product family name to "Intel Agilex 7."
2022.09.26 22.3
  • Updated chapter for new Compilation Regions tab in the Logic Lock Regions window. This read-only tab displays the properties of any Logic Lock regions contained in a .qdb file in the current project.
2022.01.07 21.4
  • Added Properties tab information to Viewing Architecture-Specific Design Information topic.
  • Added Design Assistant information to Using Logic Lock Regions in the Chip Planner topic.
  • Added new Viewing the Location and Utilization of Device Resources in Chip Planner topic.
  • Added new Viewing Module Placement by Cross-Probing to Chip Planner topic.
  • Added new Finding Design Elements in the Chip Planner topic.
  • Added new Find In Options topic.
2019.07.30 19.3.0 Added new Using User-Defined Clock Regions in the Chip Planner section.
2019.07.01 19.1.0 Added new "Snapping to a Region" topic that describes the Snap Logic Lock Region to option.
2019.04.01 19.1.0
  • Added new "Viewing Selected Contents" topic that describes a new report listing selected design elements.
2018.09.24 18.1.0
  • Added topic: Viewing Clock Sector Utilization
  • Added topic: Viewing the Source and Destination of Placed Nodes.
  • Renamed topic: Generating Fan-In and Fan-Out Connections to Viewing Fan-In and Fan-Out Connections of Placed Resources.
2018.05.07 18.0.0
  • Added recommendations for using iterative methods for floorplanning.
2017.11.06 17.1.0
  • Changed instances of LogicLock Plus to Logic Lock.
  • Added support for auto-sized Logic Lock regions.
  • Added support for empty Logic Lock regions.
  • Added topics: Considerations on Using Auto Sized Regions, Creating Partitions and Logic Lock Regions with the Design Partition Planner and Chip Planner.
2017.05.08 17.0.0
  • Chapter reorganization and content update.
  • Added figures: Clock Regions, Path List in the Locate History Window, Show Physical Routing, Using the Add Rectangle Feature, Using the Subtract Rectangle Feature, Creating a Hole in a LogicLock Region, Noncontiguous LogicLock Region, Routing Regions, Logic Placed Outside of an Empty Region.
  • Updated figures: HSSI Channel Blocks, Highlight Routing, High-Speed and Low Power Tiles in an Arria 10 Device, Show Delays Highlight Routing, Viewing Assignments in the Chip Planner, LogicLock Plus Regions Window, Using the Merge LogicLock Plus Region Command.
  • Created topics: Adding Rectangle to a LogicLock Plus Region, Subtracting Rectangle from a LogicLock Plus Region.
  • Moved topic: Viewing Critical Paths to Timing Closure and Optimization chapter and renamed to Critical Paths.
  • Renamed topic: Creating Non-Rectangular LogicLock Plus Regions to Merging LogicLock Plus Regions.
  • Renamed topic: Chip Planner Overview to Design Floorplan Analysis in the Chip Planner.
  • Renamed chapter from Analyzing and Optimizing the Design Floorplan with the Chip Planner to Analyzing and Optimizing the Design Floorplan.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Added topic describing how to create a hole in a LogicLock Plus region.
2016.05.02 16.0.0 Updated information on creating LogicLock Plus regions.
2015.11.02 15.1.0
  • Changed instances of Quartus II to Quartus Prime.
  • Added information on how to use LogicLock regions.
2015.05.04 15.0.0 Added information about color coding of LogicLock regions.
2014.12.15 14.1.0 Updated description of Virtual Pins assignment to clarify that assigned input is not available.
June 2014 14.0.0 Updated format
November 2013 13.1.0 Removed HardCopy device information.
May 2013 13.0.0 Updated “Viewing Routing Congestion” section

Updated references to Quartus UI controls for the Chip Planner

June 2012 12.0.0 Removed survey link.
November 2011 11.0.1 Template update.
May 2011 11.0.0
  • Updated for the 11.0 release.

    Edited “LogicLock Regions”

    Updated “Viewing Routing Congestion”

    Updated “Locate History”

    Updated Figures 15-4, 15-9, 15-10, and 15-13

    Added Figure 15-6

December 2010 10.1.0
  • Updated for the 10.1 release.
July 2010 10.0.0
  • Updated device support information
  • Removed references to Timing Closure Floorplan; removed “Design Analysis Using the Timing Closure Floorplan” section
  • Added links to online Help topics
  • Added “Using LogicLock Regions with the Design Partition Planner” section
  • Updated “Viewing Critical Paths” section
  • Updated several graphics
  • Updated format of Document revision History table
November 2009 9.1.0
  • Updated supported device information throughout
  • Removed deprecated sections related to the Timing Closure Floorplan for older device families. (For information on using the Timing Closure Floorplan with older device families, refer to previous versions of the Quartus Prime Handbook, available in the Documentation Archive.)
  • Updated “Creating Nonrectangular LogicLock Regions” section
  • Added “Selected Elements Window” section
  • Updated table 12-1
May 2008 8.0.0
  • Updated the following sections:

    “Chip Planner Tasks and Layers”

    “LogicLock Regions”

    “Back-Annotating LogicLock Regions”

    “LogicLock Regions in the Timing Closure Floorplan”

  • Added the following sections:

    “Reserve LogicLock Region”

    “Creating Nonrectangular LogicLock Regions”

    “Viewing Available Clock Networks in the Device”

  • Updated Table 10–1
  • Removed the following sections:

    Reserve LogicLock Region Design Analysis Using the Timing Closure Floorplan