Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.5.10. Metastability Analysis and Optimization Techniques

Metastability problems can occur when a signal is transferred between circuitry in unrelated or asynchronous clock domains, because the designer cannot guarantee that the signal meets its setup and hold time requirements. The mean time between failures (MTBF) is an estimate of the average time between instances when metastability could cause a design failure.

You can use the Intel® Quartus® Prime software to analyze the average MTBF due to metastability when a design synchronizes asynchronous signals and to optimize the design to improve the MTBF. These metastability features are supported only for designs constrained with the Timing Analyzer, and for select device families.

Synchronization identification can affect retiming. Registers that the Compiler identifies as being part of a synchronizer are not retimed. The default chain length is 3, but in some cases, a synchronizer chain is not necessary and should not be inferred. Use the report_metastability command to identify synchronizer chains that you can reduce.

For example, consider a bus that uses a synchronized enable when crossing clock domains. If you pipeline such a bus, the pipeline stages can be considered as part of a synchronizer chain, and are not used to retime the paths. Setting the chain length to 1 for these paths allows the pipeline registers to be used for retiming.