7.2.6. Example: Placement Best Practices for Intel® Arria® 10 FPGAs
This example describes how I/O Columns constrain locations in Logic Lock regions in designs targeting Intel® Arria® 10 FPGAs.
- If a Logic Lock region contains a register that interface with the I/O column, place the Logic Lock region so that the region covers the I/O column and the core logic, for better access to the I/O column adjacent to the outer column edge.
For high speed signal, you can get best results if you place the Logic Lock region on the outside of the I/O column, because the fitter is less likely to cross the column and incur delay.