Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/02/2023

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7.1.2. Chip Planner GUI

The Chip Planner GUI helps you to visualize and modify the use of device resources for your design. As you zoom in, the level of abstraction decreases, revealing more details about your design.

Chip Planner Toolbar

Figure 76. Zoom to View Device Resource Details in Chip Planner

The Chip Planner toolbar provides access to the main Chip Planner functions for visualizing and modifying device resources. Alternatively, you can access the same Chip Planner commands from the Chip Planner View menu.

Figure 77. Chip Planner Toolbar

Chip Planner Floorplan Views

The Chip Planner includes multiple views to shows various levels of detail for the targeted Intel FPGA device. You can toggle between these different views when you require more or less detail. As you zoom in to the chip, the level of abstraction decreases, revealing more details about the resources that your design targets.

Click the Bird’s Eye View button to instantly display a summary high-level chip view, on top of your current Chip Planner view. Use this Bird's Eye view to show your current selection within the larger chip, and to navigate quickly between areas of interest.

Figure 78. Bird’s Eye View

The Bird’s Eye View is particularly useful when the parts of your design that you want to view are at opposite ends of the chip, allowing you to quickly navigate between resource elements without losing the current frame of reference.

Figure 79. Selected Element Properties

When you select any element in the Chip Planner, the Properties window displays the detailed properties of the objects (such as atoms, paths, Logic Lock regions, or routing elements). To display the Properties window, right-click the object and select View > Properties.

Layers Settings Pane

clicking View > Layers Settings to customize which device structures the Chip Planner displays.

You can select the Basic, Detailed, or Floorplan Editing settings that are preconfigured for specific planning tasks, or specify your own layer settings.

Figure 80. Layer Settings Control Display of Device Resources

Editing Mode

The Chip Planner has two editing modes.

Figure 81. Editing Mode Selection

  • Assignment—editing mode allows you to make assignment changes that are implemented the next time you run the Fitter.
  • ECO—editing mode allows you to make post-compilation changes, commonly referred to as engineering change orders (ECOs), without running a full compilation.

Locate History

The Locate History window records all searches you perform using the Locate in Chip Planner command, allowing you to quickly rerun common searches.