Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/02/2023

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2.1. Initial FPGA Device Considerations

All Intel® FPGAs have a unique timing model that describes the delay information between all physical elements in the device, such as combinational adaptive logic modules, memory blocks, interconnects, and registers. The delay models comprise all valid combinations of operating condition delays for the target FPGA. The Timing Analyzer references these delay models in calculating performance during timing analysis. The device size and package determine pin-out and the resource availability. When selecting your target Intel® FPGA device for your design, you must consider the performance specifications and resources available in the device meet the needs of your design.