188.8.131.52. Physical Synthesis Optimizations
During the synthesis stage of the Intel® Quartus® Prime compilation, physical synthesis optimizations operate either on the output from another EDA synthesis tool, or as an intermediate step in synthesis. These optimizations modify the synthesis netlist to improve either area or speed, depending on the technique and effort level you select.
To view and modify the synthesis netlist optimization options, click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter).
If you use a third-party EDA synthesis tool and want to determine if the Intel® Quartus® Prime software can remap the circuit to improve performance, use the Perform WYSIWYG Primitive Resynthesis option. This option directs the Intel® Quartus® Prime software to un-map the LEs in an atom netlist to logic gates, and then map the gates back to Intel-specific primitives. Intel-specific primitives enable the Fitter to remap the circuits using architecture-specific techniques.
The Intel® Quartus® Prime Compiler optimizes the design to achieve maximum speed performance, minimum area usage, or balances high performance and minimal logic usage, according to the setting of the Optimization Technique option. Set this option to Speed or Balanced.
During the Fitter stage of the Intel® Quartus® Prime compilation, physical synthesis optimizations make placement-specific changes to the netlist that improve speed performance results for the specific Intel device.