7.5. Creating Clock Region Assignments in Chip Planner
You can create a user-defined clock region assignment to ensure that a given global clock signal is available to resources in a certain area of the device throughout all design iterations. In instances of congestion involving global signal resources, you may specify a smaller clock region assignment to prevent a signal from using congested clock resources in other sectors.
If you create user-defined clock regions and subsequently compile the design, those user-defined clock regions become Fitter-defined clock regions, and are read-only.
Summary of User-Defined Clock Region Feature Support
|Feature||Clock Region Support|
|Shapes of clock regions||Limited to rectangular regions that snap to clock sector grids.|
|Peripheral element assignments||Limited to clocking design elements.|
|Clock region name||Identified by the source clocking design element.|
|Support for multiple instances per region||Create one region per clock design element, and then specify the same definition for multiple clock design elements to assign to the same clock region.|
Using Clock Region Assignments in Intel® Stratix® 10 and Intel Agilex® 7 Devices
You can constrain clock regions to a rectangle whose dimensions are defined by the sector grid, as seen in the Clock Sector Region layer of the Chip Planner. The rectangle is defined by the coordinates of its bottom-left and top-right corners. For example, SX0, SY0, SX1, SY1 constrains the clock to a 2 × 2 region, from the bottom left of sector 0,0 to the top right of sector 1,1.
You can alternatively specify the bounding rectangle in chip coordinates, for example X37 Y181 X273 Y324. However, you should sector-align such a constraint. The Fitter automatically snaps to the smallest sector-aligned rectangle that encompasses the original assignment.