220.127.116.11. Guideline: Remove Fitter Constraints
To resolve routing congestion caused by restrictive location constraints or Logic Lock region assignments, use the Routing Congestion task in the Chip Planner to locate routing problems in the floorplan, then remove any internal location or Logic Lock region assignments in that area. If your design still does not fit, the design is over-constrained. To correct the problem, remove all location and Logic Lock assignments and run successive compilations, incrementally constraining the design before each compilation. You can delete specific location assignments in the Assignment Editor or the Chip Planner. To remove Logic Lock assignments in the Chip Planner, in the Logic Lock Regions Window, or on the Assignments menu, click Remove Assignments. Turn on the assignment categories you want to remove from the design in the Available assignment categories list.