188.8.131.52. Defining a Logic Lock Region in Chip Planner
The Chip Planner allows you to easily see Logic Lock region locations and properties in relation to other resources in the device.
Before Analysis and Elaboration, the Chip Planner displays the device floorplan resources that are available. You can define Logic Lock regions in this floorplan. After running Analysis & Elaboration, you can add member nodes to the region.
To draw a Logic Lock region in the Chip Planner:
- Open an Intel® Quartus® Prime project.
- Click Processing > Start > Start Analysis & Elaboration.
Note: You can this step if you want to reserve the empty region without adding member nodes yet.
- To open the Chip Planner, click Tools > Chip Planner. Chip Planner opens and loads device resource information.
- Click the Create Logic Lock Region button on the Chip Planner Toolbar.
Figure 109. Create Logic Lock Region Button on Toolbar
- To define the region dimensions and location, click and drag the cursor on the Chip Planner floorplan to draw a region of your preferred location and size. An <<unassigned>> Logic Lock region appears in the Chip Planner and Logic Lock Regions window at the coordinates you specify.
Figure 110. Drag Cursor to Define Region Location and Size
- In the Logic Lock Regions window, double-click <<unassigned>> and type a descriptive name for the region.
- To add member nodes to the region, click the Members cell, and then click the (…) button to search for the nodes you want to add. You must complete step 2 before this step.
Figure 111. Specifying Region Name and Members
- Confirm or customize the region Width, Height, and point of Origin settings in the Logic Lock Regions window.
- To prevent the Fitter from placing any other logic in the region, turn on the Reserved option. This option is useful for preliminary floorplanning and for reserving device resources for logic to be added later. Otherwise, leave this option off.
- To exclude periphery device resources from the region, turn on the Core-Only option.
- For region Size/State, specify whether you or the Fitter determines the size and placement of the Logic Lock region:
- If set to Fixed/Locked, the default value, you define the Logic Lock region's size and placement.
- If set to Auto/Floating, the Fitter determines the size and placement of the Logic Lock region.
- For Routing Region, specify the type of routing region constraint, such as Unconstrained, Whole Chip, or Fixed Width Expansion options. Refer to Defining Routing Regions.