22.214.171.124. Evaluate Wires Added for Hold
Review the specific register paths in the Estimated Delay Added for Hold Timing report to determine whether the Fitter adds excessive wire to meet hold timing.
An example of an incorrect constraint which can cause the router to add wire for hold requirements is when there is data transfer from 1x to 2x clocks. Assume the design intent is to allow two cycles per transfer. Data can arrive any time in the two destination clock cycles by adding a multicycle setup constraint as shown in the example:
set_multicycle_path -from 1x -to 2x -setup -end 2
The timing requirement is relaxed by one 2x clock cycle, as shown in the black line in the waveform in the figure.
set_multicycle_path -from 1x -to 2x -setup -end 2 set_multicycle_path -from 1x -to 2x -hold -end 1
The orange dashed line in the figure above represents the hold relationship, and no extra wire is required to delay the data.
The router can also add wire for hold timing requirements when data transfers in the same clock domain, but between clock branches that use different buffering. Transferring between clock network types happens more often between the periphery and the core. The following figure shows data is coming into a device, a periphery clock drives the source register, and a global clock drives the destination register. A global clock buffer has larger insertion delay than a periphery clock buffer. The clock delay to the destination register is much larger than to the source register, hence extra delay is necessary on the data path to ensure that it meets its hold requirement.
To identify cases where a path has different clock network types, review the path in the Timing Analyzer, and check nodes along the source and destination clock paths. Also, check the source and destination clock frequencies to see whether they are the same, or multiples, and whether there are multicycle exceptions on the paths. Finally, ensure that all cross-domain paths that are false by intent have an associated false path exception.
If you suspect that routing is added to fix real hold problems, you can disable the Optimize hold timing advanced Fitter setting (Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) > Optimize hold timing). Recompile the design with Optimize hold timing disabled, and then rerun timing analysis to identify and correct any paths that fail hold time requirements.