AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents Qsys System and Components

Figure 7. Qsys System and Components for Design Example 3The C code program in the Nios® II processor controls the fPLL reconfiguration IP core. This program consists of a simple loop that receives and executes command from the JTAG UART.