AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters

The design example uses a 5SGXEA7 device. This design example consists of the Altera PLL and Altera PLL Reconfig IP cores. The fPLL synthesizes two output clocks of 233.34 MHz, with 0 ps and 107 ps phase shift on C0 and C1 output respectively. The input reference clock to the fPLL is 100 MHz.

The Altera PLL Reconfig IP core connects to a state machine to perform the required Avalon® write and read operations. A low pulse on the reset_SM pin starts the Avalon write and read sequence. After reconfiguration, the fPLL operates with the following configuration:

  • M counter = 36
  • MFRAC = 0.2665
  • N counter = 4
  • C0 = 6 (high_count = 3, low_count = 3, even division)
  • C1 = 8 (high_count = 4, low_count = 4, even division)
  • Bandwidth setting = 0110 (for medium bandwidth)
  • Charge pump setting = 010 (for medium bandwidth)

To run the test with the design example, perform these steps:

  1. Download and restore the pll_reconfig_mnc.qar file.
  2. Regenerate the Altera PLL and Altera PLL Reconfig instances in the design.
  3. Change the pin assignment and I/O standard of the design example to match your hardware.
  4. Recompile your design. Ensure that your design does not contain any timing violation after recompilation.
  5. Open the SignalTap™ II File (.stp) and download the SRAM Object File (.sof).
  6. Provide a low pulse on the reset_SM input pin to start the reconfiguration.
    The expected C0 output frequency is 151.11 MHz and the expected C1 output frequency is 113.33 MHz.

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