AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Public
Document Table of Contents

1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift

This design example is similar to “Design Example 1”, except that this design example demonstrates the dynamic phase shift feature of the fPLL with the Altera PLL Reconfig IP core. A low pulse on the reset_SM pin starts the Avalon write and read sequence to dynamically phase shift the PLL output. After completing the dynamic phase shifting successfully, the C1 output is phase-shifted for four forward steps.

To run the test with the design example, perform these steps:

  1. Download and restore the pll_reconfig_dps.qar file.
  2. Regenerate the Altera PLL and Altera PLL Reconfig instances in the design.
  3. Change the pin assignment and I/O standard of the design example to match your hardware.
  4. Recompile your design and ensure your design does not contain any timing violation after recompilation.
  5. Open the .stp file and download the .sof file.
  6. Provide a low pulse on the reset_SM input pin to start the reconfiguration.