AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

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ID 683640
Date 10/14/2019
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Document Table of Contents
Document Table of Contents x
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores x
1.1. Fractional PLL Reconfiguration in 28-nm Devices 1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software 1.3. Design Considerations 1.4. Using the Design Examples 1.5. Tutorial Walkthrough 1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1.1. Fractional PLL Reconfiguration in 28-nm Devices x
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software x
1.1.1.1. Connectivity between Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.2. Connecting Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core 1.1.1.4. Registers and Counters Settings 1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface 1.1.1.6. .mif Streaming Reconfiguration
1.1.1.4. Registers and Counters Settings x
1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings 1.1.1.4.2. Counter Address and Bit Setting During Read Operation 1.1.1.4.3. Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting
1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface x
1.1.1.5.1. Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface
1.1.1.6. .mif Streaming Reconfiguration x
1.1.1.6.1. Stitching Two .mif Files Generated by the Intel® Quartus® Prime Software 1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core 1.1.1.6.3. .mif File Format 1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes
1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software x
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core 1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core x
1.2.1.1. Waveform Example for Dynamic Phase Shift with Altera PLL IP Core 1.2.1.2. Dynamic Phase Shift Signals in Altera PLL IP Core 1.2.1.3. Logical Counter Bit Setting
1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core x
1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core
1.4. Using the Design Examples x
1.4.1. Software Requirement 1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters 1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift 1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow 1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core 1.4.6. Design Example 5: .mif Streaming Reconfiguration
1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow x
1.4.4.1. Qsys System and Components 1.4.4.2. Main Menu Commands in Qsys 1.4.4.3. Submenu Commands in Qsys
1.5. Tutorial Walkthrough x
1.5.1. Creating a New Intel® Quartus® Prime Project 1.5.2. Creating the Qsys System 1.5.3. Creating the Top-Level Design File 1.5.4. Incorporating the Nios II SBT for Eclipse 1.5.5. Verifying Design on Hardware
1.5.4. Incorporating the Nios II SBT for Eclipse x
1.5.4.1. Adding Test Code to the Nios II SBT for Eclipse 1.5.4.2. Setting Up the Nios II Project Settings
1.5.5. Verifying Design on Hardware x
1.5.5.1. Compiling the Project 1.5.5.2. Downloading the Object File 1.5.5.3. Verifying Design with the Nios II SBT for Eclipse
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings

Table 2.  Fractional PLL Dynamic Reconfiguration Registers and Settings
Register Name Register Size Address (Binary) Counter Bit Setting Read/Write
Mode Register 1 000000
  • Write 0 for waitrequest mode
  • Write 1 for polling mode
Read/Write
Status Register 1 000001
  • 0 = busy
  • 1 = ready
Read
Start Register 1 000010 Write either 0 or 1 to start fractional PLL reconfiguration or dynamic phase shift Write
N Counter 18 000011
  • N_counter[7:0] = low_count
  • N_counter[15:8] = high_count
  • Total_div = high_count + low_count
  • N_counter[16] = bypass enable 1
    • N_counter[16] = 0, fREF = fIN/Total_div
    • N_counter[16] = 1, fREF = fIN (N counter is bypassed)
  • N_counter[17] = odd division 1
    • N_counter[17] = 0, even division, duty cycle = high_count/Total_div
    • N_counter[17] = 1, odd division, duty cycle = (high_count – 0.5)/Total_div
Read/Write
M Counter 18 000100
  • M_counter[7:0] = low_count
  • M_counter[15:8] = high_count
  • Total_div = high_count + low_count
  • M_counter[16] = bypass enable 1
    • M_counter[16] = 0, fFB = fVCO/Total_div
    • M_counter[16] = 1, fFB = fVCO (M counter is bypassed)
  • M_counter[17] = odd division 1
    • M_counter[17] = 0, even division, duty cycle = high_count/Total_div
    • M_counter[17] = 1, odd division, duty cycle = (high_count – 0.5)/Total_div
Read/Write
C Counter 23 000101
  • C_counter[7:0] = low_count
  • C_counter[15:8] = high_count
  • Total_div = high_count + low_count
  • C_counter[16] = bypass enable 1
    • C_counter[16] = 0, fOUT = fVCO/Total_div
    • C_counter[16] = 1, fOUT = fVCO (C counter is bypassed)
  • C_counter[17] = odd division 1
    • C_counter[17] = 0, even division, duty cycle = high_count/Total_div
    • C_counter[17] = 1, odd division, duty cycle = (high_count – 0.5)/Total_div
  • C_counter[22:18] is a five bit binary number ranging from 00000 to 10001 (0–17) to select which C counter to change. For example, if you want to change C2, set C_counter[22:18] to 00010.
Read/Write 2
Dynamic_Phase_Shift 22 000110
  • Dynamic_Phase_Shift[15:0] = number of shifts
    • Number of shifts = the number of times you want to shift the output clock. Every time you perform a shift, the actual amount of shift is 1/8 of the VCO period. For example, if the VCO is running at 1.6 GHz, each phase shift equals to 78.125 ps.
  • Dynamic_Phase_Shift[20:16] = cnt_select.
    • cnt_select is a five bit value that specifies which counter output is shifted. For more information about cnt_select mapping, refer to the Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting table.
  • Dynamic_Phase_Shift[21] = up_dn
    • up_dn = The direction of the shift.
    • up_dn = 1 (positive phase shift).
    • up_dn = 0 (negative phase shift).
Write
M Counter Fractional Value (K) 32 000111 Fractional part of the M counter (for DSM). The actual fractional values are:
  • MFRAC=K[(X-1):0]/2 X (X = 8, 16,24, or 32) 3
  • M counter final value = Total_div for M Counter + MFRAC
Write
Bandwidth Setting 4 001000 For the bandwidth settings, refer to the PLL Reconfiguration Calculator. Read/Write
Charge Pump Setting 3 001001 For the charge pump settings, refer to the PLL Reconfiguration Calculator. Read/Write
VCO Post Divide Counter Setting 4 1 011100 Enable or disable /2 divider for VCO to keep VCO frequency in operating range.
  • 0: VCO DIV = 2
  • 1: VCO DIV = 1
Read/Write
.mif Base Address 9 011111 Base address for the start of a PLL profile in a Memory Initialization File (.mif). Write
Related Information
1 The bypass enable bit, even division bit, and odd division bit of the M, N, and C counters support write operation only.
2 For C counter read operation, use the address for the selected counter in the Counter Address and Bit Setting During Read Operation table.
3 K counter reconfiguration is effective only when you configure the PLL in fractional mode prior to reconfiguration. For optimum performance, set the MFRAC value between 0.05 and 0.95. X = fractional carry bit, determined in the Altera PLL parameter editor. The default value for X is 24 and cannot be reconfigured during PLL reconfiguration.
4 The VCO frequency reported by the Intel® Quartus® Prime software takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
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