AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.5.2. Creating the Qsys System

To create a Qsys system, follow these steps:

  1. On the Tool menu, click Qsys.
  2. Add the Qsys components that your design requires.
    1. To create an Altera PLL instance, perform these steps:
      1. Expand PLL, select Altera PLL, and click Add.
      2. Set Reference Clock Frequency to 50.0 MHz.
      3. Select the number of output clock and set its output frequency and phase relationship.
      4. In the Settings tab, turn on the Enable dynamic reconfiguration of PLL option.
      5. Click Finish.
    2. To create an Altera PLL Reconfig instance, perform these steps:
      1. Expand PLL, select Altera PLL Reconfig, and click Add.
      2. Click Finish.
    3. Under Component Library > Memories and Memory Controllers > On-Chip, select On-Chip Memory (RAM or ROM), and then click Add.
      1. For Total Memory size, type 65536 bytes.
      2. Click Finish.
    4. Under Component Library, expand Embedded Processors, select Nios II Processor and click Add.
      1. Select Nios II/s.
      2. Set Reset Vector Offset to 0x00 and Exception Vector Offset to 0x20.
      3. Click Finish.
    5. Under Interface Protocols > Serial, select JTAG UART and click Add.
      1. Under Write FIFO and Read FIFO, for the Buffer depth (bytes) select 64, and for IRQ threshold type 8.
      2. For Prepare interactive windows, select INTERACTIVE_INPUT_OUTPUT to open the interactive display window during simulation.
      3. Click Finish.
    6. In the Project Setting tab, for Clock Crossing Adapter Type, select Auto.
  3. In the System Contents tab, make the appropriate bus connection and IRQ lines as shown in Qsys System and Components for Design Example 3 figure.
    If there are warnings about overlapping addresses, on the System menu, click Assign Base Addresses. If there are warnings about overlapping IRQ, on the System menu, click Assign Interrupt numbers.
  4. After setting up the connections, right-click the Nios II Processor and select Edit to open the Nios II Processor parameter editor. In the Core Nios II tab, for Reset vector memory and Exception vector memory, select onchip_memory2_0.s1, and click Finish.
  5. On the File menu, click Save.
  6. In the Generation tab, under Synthesis, turn on Create HDL design files for synthesis and Create block symbol file (.bsf).
  7. Click Generate.