AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.1. Fractional PLL Reconfiguration in 28-nm Devices

The fPLLs in 28-nm devices also support integer PLL. fPLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The fPLLs in 28-nm devices support dynamic reconfiguration. While the device is in user mode, you can download a new fPLL configuration in real time without reconfiguring the entire FPGA.

The following fPLL components are reconfigurable in real time using the dynamic reconfiguration IP core:

  • Post-scale output counter (C)
  • Feedback counter (M)
  • Prescale counter (N)
  • Charge pump current (ICP), and loop-filter components (R, C)
    Note: The Intel® Quartus® Prime software version 12.0 and later support ICP, R, and C reconfiguration.
  • Dynamic phase shifting of each counter
  • Fractional division (MFRAC) for Delta Sigma Modulator (DSM)

Applications that operate at multiple frequencies can benefit from fPLL reconfiguration in real time. fPLL reconfiguration is also beneficial in prototyping environments, allowing you to sweep fPLL output frequencies and adjusting the clock output phase at any stage of your design. You can also use this feature to adjust clock-to-out (tCO) delays in real time by changing the output clock phase shift.