AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents Verifying Design with the Nios II SBT for Eclipse

To verify your design with the Nios II SBT for Eclipse, perform these steps:

  1. Right-click on <project>, point to Run As, and click Nios II Hardware for the Nios II C/C++ Eclipse to compile the example test program.
  2. Type in your selection to test your system.