AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Public
Document Table of Contents

1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core

The control interface for the Altera PLL Reconfig IP core is an Avalon®-MM slave interface, which the master user logic controls. External user logic uses these Avalon ports to reconfigure the fractional PLL settings directly.

Table 1.  Avalon-MM Signals in Altera PLL Reconfig IP CoreLogic are sampled with rising edge of the clock. The first rising edge after deassertion of the waitrequest signal samples a read or write command.
Port Direction Description
mgmt_read_data[31:0] Output Data read from the Altera PLL Reconfig IP core when you assert the mgmt_read signal.
mgmt_write_data[31:0] Input Data written to the Altera PLL Reconfig IP core when you assert the mgmt_write signal.
mgmt_address[5:0] Input Specifies the address of the memory mapped register for a read or write operation.
mgmt_read Input Active high signal. Asserted to indicate a read operation. When present, read data is available on the mgmt_read_data bus.
mgmt_write Input Active high signal. Asserted to indicate a write operation. When present, the mgmt_write_data bus requires write data.
mgmt_reset Input Active-high signal that resets all PLL settings to their initial .sof file values.
mgmt_waitrequest Output Active high signal. When the Altera PLL Reconfig IP core asserts this signal, the IP core ignores read or write operations.

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