AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Public
Document Table of Contents

1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core

Figure 3. Altera PLL Reconfig IP Core with .mif Streaming Enabled

.mif streaming is a subsystem generated in the Altera PLL Reconfig IP core. If you set the Enable MIF Streaming option to 0, .mif streaming is not generated and the top level module's ports map directly to the Altera PLL Reconfig IP core. If you set the Enable MIF Streaming option to 1, the .mif reader is instantiated in the top-level of the Altera PLL Reconfig module.

When you write to the .mif Base Address register and starts the .mif streaming operation, the Altera PLL Reconfig IP core signals the .mif reader to begin the operation. waitrequest signal is asserted until the operation is complete.

.mif streaming switches the Altera PLL Reconfig IP core to waitrequest mode and asserts the waitrequest signal until the IP core completed the operation. At this point, .mif streaming restores the previous mode (waitrequest or polling), unless it is explicitly changed by the .mif file.