AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow

The design example for fPLL reconfiguration uses the Qsys design flow, targeting the 5SGXEA7 device. The fPLL synthesizes four output clock of 106 MHz with 0 ps, 168 ps, 336 ps, and 505 ps on C0, C1, C5, and C10 output respectively. The input frequency of the fPLL is 50 MHz.

To run the test with the design example, perform these steps (enter submenu):

  1. Download and restore the pll_reconfig_qsys.qar file.
  2. Change the pin assignment and I/O standard of the design example to match your hardware.
  3. Regenerate the Qsys system in the design example.
  4. Recompile your design and ensure your design does not contain any timing violation after recompilation.
  5. Open the .stp file and download the .sof file.
  6. Launch the Nios® II Software Build Tools (SBT) for Eclipse to set up the Nios® II project and compile the test program.
  7. Download the Executable and Linking Format File (.elf) to run the example test.