AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Public
Document Table of Contents

1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core

Figure 6. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core

The operation of the waveform example is as follows:

  1. Avalon writes to the mode register (address=0x00) to set the Altera PLL Reconfig IP core to operate in polling mode.
  2. Avalon writes to the dynamic phase shift register (address=0x06) to perform dynamic phase shift on C1 counter for four steps forward.
  3. Avalon writes to the start register (address=0x02) to start dynamic phase shifting.
  4. Avalon reads from the status register (address=0x01) until a value of 1 has been read from the status register, indicating the dynamic phase shifting is complete.