AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents Compiling the Project

To compile your project, follow these steps:

  1. Add SignalTap II Logic Analyzer to your design. The SignalTap II Logic Analyzer shows read and write activity in the system.
  2. After adding signals to the SignalTap II Logic Analyzer, you can recompile your design. To recompile your design, on the Processing menu, click Start Compilation.
  3. After compilation, ensure that the TimeQuest timing analysis passes successfully.
  4. Connect your hardware to your computer.