AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.5.3. Creating the Top-Level Design File

You can consider the Qsys system as a component in your design. The Qsys system can be the only component or one of many components. Hence, when your Qsys system is complete, you must add the system to your top-level design.

The top-level design can be in your preferred HDL language or a .bdf schematic design.

In this walkthrough, the top-level design is a simple wrapper file around the Qsys system with no additional components. The top-level design defines only the pin naming convention and port connection.

Figure 8. Qsys Top-Level Block Diagram

To create a top-level design for your Qsys system with a .bdf schematic, follow these steps:

  1. In the Intel® Quartus® Prime software, on the File menu, click New.
  2. Select the Block Diagram/Schematic file and click OK.
    A blank .bdf, Block1.bdf, opens.
  3. On the File menu, click Save as. In the Save As dialog box, click Save.
    The Intel® Quartus® Prime software sets the .bdf file name to your project name automatically.
  4. Right-click in the blank.bdf, point to Insert and click Symbol to open the Symbol dialog box.
  5. Expand Project, under Libraries select system, click OK.
  6. Add system.qip to the project.
  7. Connect the reconfig_to_pll[63:0] bus on the Altera PLL Reconfig instance to the reconfig_to_pll[63:0] bus on the Altera PLL instance.
  8. Connect the reconfig_from_pll[63:0] bus on the Altera PLL instance to the reconfig_from_pll[63:0] bus on the Altera PLL Reconfig instance.
  9. Position the Qsys system component and click Generate pins for Symbol Ports to automatically add pins and nets to the schematic symbol.
  10. Rename the existing pins to the modified pin names as follows:
    Existing Pin Name Modified Pin Name
    clk_clk inclk
    reset_reset_n reset_n
    pll_0_reset_reset areset
    pll_0_locked_export locked
    pll_0_outclk0_clk co_ouput
    pll_0_outclk1_clk c1_ouptut
    pll_0_outclk10_clk c10_ouptut
    pll_0_outclk5_clk c5_output
  11. Connect the pll_refclk_clk port to the inclk pin.
  12. On the File menu, click Save.
  13. On the Project menu, click Set as Top-Level Entity.
  14. Assign the I/O standard and pin locations for all pins in your design.
  15. Add the timing constraint to the .sdc file to constrain the input clock of your design.
  16. Compile your design.