AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core

You can directly perform dynamic phase shift by enabling the dynamic phase shift ports. To perform one dynamic phase shift, follow these steps:

  1. Set the updn and cntsel ports.
  2. Assert the phase_en port for at least two scanclk cycles. Each phase_en pulse enables one phase shift.
  3. Deassert the phase_en port after phase_done goes low.
The updn, cntsel, and phase_en ports are synchronous to scanclk. The phase_done signal going low is synchronous to the scanclk signal, but it is asynchronous to the scanclk signal when going high. Depending on the VCO and scanclk frequencies, the low time of the phase_done port may be greater than or less than one scanclk cycle. Each phase_en pulse enables one phase shift. If you want to perform multiple phase shifts, you must assert the phase_en signal multiple times. You can only assert the phase_en signal after the phase_done signal goes from low to high.