AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents .mif Streaming Reconfiguration Operation Codes

Table 5.  .mif Streaming Reconfiguration Operation Codes
Operation Name Operation Code Description
Start of .mif (SOM) 111110 Indicates start of single PLL configuration
End of .mif (EOM) 111111 Indicates end of single PLL configuration

Each .mif streaming reconfiguration must be indicated with a SOM and EOM opcodes.

The remaining opcodes are the addresses for each of the registers in the Altera PLL Reconfig IP core.

You can save multiple PLL configurations in a .mif file if you mark the SOM or EOM opcodes appropriately. The .mif reader reads the settings from an M20K RAM block, which has default address width = 9 bits, data width = 32 bits (total words = 512). These sizes can change as parameters are passed to the top-level module. For .mif streaming reconfiguration, data width must be 32 bits to match the Altera PLL Reconfig IP core.

The M20K is initialized by MIF_FILE_NAME, also a top-level parameter. On the start of .mif streaming operation, the .mif reader checks the .mif base address in the M20K RAM block for a SOM opcode. The .mif reader continues to read the file until EOM opcode is reached.

You can generate a .mif file independently with a PLL .mif configuration file generated by the Altera PLL parameter editor. The generated .mif file stores the entire PLL profile.

You can also construct your own .mif files by stitching together existing .mif files or writing your own commands (following the .mif syntax). This allows what settings are stored in the M20K for future reconfiguration.