AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.4.6. Design Example 5: .mif Streaming Reconfiguration

This design example is similar to “Design Example 1”, except that this design example demonstrates the .mif streaming reconfiguration of the fPLL with the Altera PLL Reconfig IP Core. This design example consists of the Altera PLL and Altera PLL Reconfig IP cores. The fPLL synthesizes two output clocks of 200.0 MHz, with 0 degree and 7.5 degree phase shift on C0 and C1 output respectively. The input reference clock to the fPLL is 100 MHz.

A low pulse on the reset_SM pin starts the Avalon® write operation to enable the .mif streaming reconfiguration. After completing the .mif streaming reconfiguration, the C0 and C1 output frequencies are changed to 100 MHz and 300 MHz respectively.

To run the test with the design example, perform these steps:

  1. Download and restore the pll_mifstreaming.qar file.
  2. Regenerate the Altera PLL and Altera PLL Reconfig instances in the design.
  3. Change the pin assignment and I/O standard of the design example to match your hardware.
  4. Recompile your design and ensure your design does not contain any timing violation after recompilation.
  5. Open the stgkp.stp file and download the .sof file.
  6. Provide a low pulse on the reset_SM input pin to start the reconfiguration.