AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents .mif Streaming Reconfiguration

.mif streaming allows you to dynamically reconfigure PLLs through the Altera PLL Reconfig IP core using predefined settings saved in an on-chip RAM.

To start reconfiguration via .mif streaming, follow these steps:

  1. Write the base address in the ROM where the .mif file of the PLL is located.
    You can have multiple .mif files in a ROM. You just need to use a different address location in the ROM for another .mif streaming as follows:
    • Writedata = base address in ROM.
    • Write address = .mif address (011111).
  2. Write to the Start register to begin.
  3. The Altera PLL Reconfig IP core then starts reading the .mif file for new settings and values, changing the PLL accordingly.
  4. The Altera PLL Reconfig IP core generates signals when all changes are done and PLL is locked.