AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

ID 683640
Date 10/14/2019
Document Table of Contents

1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core

This design example is only supported by the Intel® Quartus® Prime software version 13.1 and later due to IP upgrade from physical counter to logical counter.

This design example uses a 5SGXEA7 device. This design example consists of the Altera PLL IP core. The fPLL synthesizes two output clocks of 233.34 MHz, with 0 ps and 107 ps phase shift on C0 and C1 outputs, respectively. The input reference clock to the fPLL is 100 MHz. The Altera PLL IP core connects to a state machine to perform direct dynamic shift operation. A low pulse on the rest_sm pin starts the direct dynamic phase shift sequence.

To run the test with the design example, follow these steps:

  1. Download and restore pll_dynamicphaseshift.qar file.
  2. Regenerate the Altera PLL instances in the design.
  3. Change the pin assignment and I/O standard of the design example to match your design.
  4. Recompile the design and ensure that the design does not contain any violation after compilation.
  5. Open the .stp file and download the .sof file.
  6. Provide a low pulse on the reset_sm input pin to start the dynamic phase shift.