Arria 10 GX Transceiver Signal Integrity Development Kit User Guide
ID
683553
Date
8/08/2017
Public
A.1. CFI Flash Memory Map
A.2. Preparing Design Files for Flash Programming
A.3. Creating Flash Files Using the Nios II EDS
A.4. Programming Flash Memory Using the Board Update Portal
A.5. Programming Flash Memory Using the Nios II EDS
A.6. Restoring the Flash Device to the Factory Settings
A.7. Restoring the MAX V CPLD to the Factory Settings
6.4.5.1. Status
The Status control displays the following status information during the loopback test:
- PLL lock—Shows the PLL locked or unlocked state.
- Pattern sync—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.
- Details - Shows the PLL lock and pattern sync status.